How to design for Timing Efficieny in FPGA ....what to do ...where to start ????

Question

I have played with FPGA's a little .... I have done small digial circuits in Verilog or VHDL also. One thing that bothers me still and I have not been able to find concrete examples or a pathway to follow is Timing.

I don't know how to use various constarints and how to make designs time-efficient

Do reply or give any references/ links as to how I should proceed.

Answer 1

Look at your tool documentation to see how to use timing constraints.

Start by building your logic in some way that makes sense. If it already meets your timing requires (after place & route), you're golden. If you're off by a little, add timing constraints to the PAR step, and use synthesis options (see your tool documentation again) that favor speed over gate count. If you're off by a lot, determine whether your problem is logic latency or wire delay - maybe you can move registers around to equalize latencies between them, or add pipelining registers.

Answer 2

One of the problems with FPGAs compared with PALs and CPLDs is that timing is non-determinant until after place-and-route. In fact, the same synthesized design can be placed-and-routed 10 times resulting in 10 different timing sets.

This is why timing is such a difficult issue with FPGAs and why there is no good concrete answer to the question.

Different FPGA manufacturers have different philosophies and methodologies in how timing is handled. I have used FPGAs from Xilinx, Actel, and Quicklogic (and CPLDs from Altera where timing is determinant).

Even the synthesis tool cannot give the place-and-router enough information to make timing determinant. In general you trade gate efficiency with timing efficiency, but even the makers of the synthesis tools have their own philiosophies and methodologies for trade-offs (again, leaving timing indeterminant).

The best answer I can give is to link to the manufacturer of the FPGA you are using and study their application notes on timing constraints.

If it is Xilinx you are using, edit your answer (additional details) affirming this. I can look through their site (because I am familiar with it) and link some of these app. notes. Also, what synthesis tool are you using?

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