Asyncrhronous (ripple) counters.?

Question

For my lab, we built a ripple counter by hooking the output to the clock of the next JK Filp Flop. Since the rest are unconnected, they all are a vaule of high (or 1 or True or on etc.)

Starting at 0 0 0 0 ( a four bit counter)

When the clock0 goes to 0 to 1, we get 1 for the Q0 on the first bit. Since, Q0 goes from 0 to 1, the Q1 remains the same meaning zero.

Now here's my problem... what is the logic for the remaining bits? My assumpition is since Q1 (or clock2) remains the same, the previous state remains.

So, the main part of the logic is just based the first few bits.

Answer 1

You have to use standard nomenclature for your logic problem. With a jk f/f there is clock, set steering, reset-steering, Q and Not Q.