Cmos design method?

Question

i am a student taking the subject of "ic design".
as far as i know, in static cmos design, the pull up network and pull down network do not have the same structure. if the pull up network implements the function F, then the pull down network will impliment the function F bar.
but from the library of the design software, i saw a design where the pull up network has the structure same as the pull down network. both the network is facing each other like a mirror. i can't figure out how it work.
how can i get a boolean equation from this? can someone help me out?
thx

Answer 1

Your problem seems that your observation level is wrong for your logical reasoning level. You need to take your observation level either up one layer to the circuit-model level, or down one layer to the dope-profile level.

The layouts look the same for both P-MOS pull-up and N-MOS pull-down. But the circuit model should show two different transistors (center arrow pointing inwards on the pull-up, and outwards on the pull-down). And the dope-profile level would likely show Boron on the pull-up and Phosphorous on the pull-down.

Actually if you looked more closely you should see the pull-up having transistor feature size about twice wider than the pull-down feature size. This reminds that the mobility of electrons is faster than that of holes, and that, for example, a NAND gate is cheaper to implement in CMOS than an AND gate.

Answer 2

Hi - started to answer your question and after a few hundred words, I re-read what sciquest had put. Spot on - go with that - check the level you are working at... (my advice don't go deeper than you have to!!)