English Deutsch Français Italiano Español Português 繁體中文 Bahasa Indonesia Tiếng Việt ภาษาไทย
All categories

Does anyone know what this code is in gates leves?
like change in to gates, AND gates etc!

module IOcont(DIN, RESET,CLK, serial_IO, AddrOut, chipSel,DataOut);
input RESET; //The reset signal.
input CLK; //clock
input serial_IO; // The serial port through which communication to the external
// system occurs.

input chipSel; // This is the handshaking signal from the external system telling the
// input IO controller that it is ready to send data

input[13:0] DIN; // A signal from the processor which tells the input
// IO controller to receive data from the external signal

output [13:0] AddrOut; // The 14 bit data is converted into a parallel 14 bit data,
// then stored in AddrOut register.

output [2:0] DataOut;

reg [13:0] AddrOut;

always begin
if(chipSel == 1)begin
AddrOut = DIN;
end
else begin
AddrOut = AddrOut;
end
end

endmodule

2007-12-05 07:29:03 · 2 answers · asked by Anonymous in Science & Mathematics Engineering

2 answers

What amansscientiae says is correct.

The always block is a 13-bit wide latch -- nothing more. This should be compiled in Verilog2000, not Verilog93, because the argument list after the always statement is not there.

2007-12-05 09:31:34 · answer #1 · answered by tlbs101 7 · 0 0

Looks pretty incomplete to me. If it is supposed to be a 14 bit wide latch for DIN, I'd be scared to look at what the rest of the code looks like. If it was supposed to be a 14 bit wide 2-to-1-Mux, it's just plain wrong.

The comments make no sense whatsoever. I don't see any serial to parallel conversion. Buses are labeled signals... why?

I also don't see how several of the signals are supposed to be used in this module. It looks like as if the designer got started and then abandoned the code at approx. 10% completion level.

Having said that... I am an FPGA kind of guy and my VHDL is coded the same way as my C++, Java and Python: lean and clean and always deterministic. So I would not write this thing this way... but I know that a chip designer will do things differently because latches etc. are way less scary if you know your tools, especially what the compiler will make of it on the lowest level.

Hope you did not pay someone money for this code.

:-)

2007-12-05 07:52:43 · answer #2 · answered by Anonymous · 0 0

fedest.com, questions and answers