are you familiar with BJT transistors, parasitic capacitance, break frequencies for bode plots?

Question

I cannot find an example in the book like this. Say you have a BJT transistor amplifier (common emitter) configuration WITHOUT the bypassed emitter resistor. When you take into the account the parasitic capacitance, you use the miller effect to drop Ccb down to the base to ground and the collector to ground. If the emitter resistor WAS bypassed, you would add these miller-capacitances to their closest parasitic capacitance since they're in parallel, right? Well since the emitter resistor ISN'T bypassed, you should treat the two separate to find the break frequencies (1/(2*pi*C*Rthevenin)) since they're not in parallel and you can't combine. IS THIS CORRECT? BY "THIS" I MEAN TREATING THE MILLER AND THE PARASITIC CAPACITANCE SEPARATELY AND GETTING MULTIPLE BREAK FREQUENCIES?

Answer 1

There are 3 frequency ranges where these capacitances are in effect: low, mid, and high. At low frequencies the Miller capacitance and the Cpi (Cbe) capacitances are essentially open circuits, while the emitter bypass is a very low impedance. At mid frequencies, all capacitances act like open circuits. At high frequencies the emitter bypass acts like a open circuit, while the Miller capacitance (in parallel with Cpi) are dominant.

So, there are 2 breakpoints, but at both ends of the spectrum. The low frequency breakpoint for a bypassed emitter CE amp is dominated by the AC coupling capacitor, if the emitter bypass cap is made large enough. The other breakpoint at the high end, is dominated by Cm+Cpi.

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Answer 2

From a practical perspective, if you have a circuit where you are worried about Miller capacitance, you cascode. I design preamplifiers for a living and I always cascode... there is little use for an amplifier in today's world that isn't. Having said that, if the circuit that follows after the input stage has plenty of gain (like an opamp) AND you are running closed loop, the opamp will act like a cascode by suppressing the collector voltage variations by its open loop gain.

I rarely ever worry about the detailed calculations of parasitic effects as long as I can get away with a spice simulation. To figure it out numerically is faster, cheaper and usually more reliable than first order circuit approximations on paper. And because you can simply drop in simulated Miller capacitances, you can see easily how far the poles of the transfer function move and which effect is dominant.

To get back to your question, the mapping between parasitics and poles/zeros is complicated. Every additional capacitive or inductive element will move ALL poles and zeros and create a new one. Trying to figure it out in closed form in a real world circuit is possible but rarely informative (there are very famous counterexamples). The analog designers I work with typically rely on their experience and intuition to figure out the leading cause of a problem and then use numerical simulation to optimize it. The first part is the hard part because often the leading problem is not the suspected one and then a lot of time is wasted on "curing a non-life threatening disease while the patient is dying".

Just my two cents.

Answer 3

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