Circuit Design Again...?

Question

I would like to know the schematic (using logic gates) for a circuit that can delay a clock signal by quarter of it's wavelength (Out of phase by 90 degree).

Answer 1

You should know your clock pulse width. Use a single-shot timed for 1/4 the pulse width. Run the SS output through a NOT gate, and AND it with the original clock pulse. This will give you a 3/4 width pulse delayed by 1/4 pulse width.

Answer 2

If you know the frequency of the clock, then obtain another one 16x faster (or 8x faster), and use a shift register to shift in your clock signal (running the shift register 16x faster than your signal). Tap off the Q output of the 4th flip-flop in the register and there you have your 90-degree shifted signal.

If you use an 8x clock for the shift register, tap off the 2nd fliop-flop, but your absolute time error for the 90 degree phase output will be greater than if you use a 16x clock.

It would also help if you put a single D flip-flop in front of the input to the shift register, to reduce metastability in the shift register. This applies to both the 8x and 16x clocks.

.