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I'm doing a project on silicon and transistors. I've come to the section about 3D transistors (basically using more than one gate). The question is does 3d transistor have any effect on subtreshold leakage of the transistor?

2007-04-13 03:02:28 · 1 answers · asked by hOsEiN m 2 in Science & Mathematics Engineering

1 answers

Sure. There's a longer source to drain path plus the channels are broken into sections which should reduce the leakage current between those two terminals since the electric field there is spread over a longer distance. Gate leakage should be about the same since it's mostly tunneling. Here's a nice writeup.

http://www.tomshardware.co.uk/2006/12/04/infineon_multi_gate_transistor/

2007-04-13 03:12:24 · answer #1 · answered by Gene 7 · 0 0

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