what is meant by skew rate in digital circuits??

Question

CMOS digital integrated circuits

Answer 1

Skew is a time difference. I've never heard of is as a 'rate' before.

Clock signals ideally arrive at clock pins (or clock signal inputs in integrated flip flops) simultaneously. in the real world, that doesn't happen. Different wire lengths, trace lengths, or metallization lengths (electrical 'length' includes capacitive and inductive effects) will cause the clock rising edge to arrive at different times to different flip-flops. This time difference is the skew.

However, this only becomes important for certain types of sequential circuits -- long chain shift registers and ripple counters. For wide ripple counters (say 12-bit and up) not only does the clock period have to be greater than the total time for the result to ripple through the chain, but if the clock skew is so bad that some flop in the middle of the chain gets the rising edge before the first flop, you will end up with errors.

The middle flop will "go", then (skew time later) the first flop will "go", but by the time the ripple reaches the middle flop, a hold violation has occurred -- error!

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Answer 2

I believe that also referred to as propogation delay. Propogation delay is the phenomenon where the output of the gate will be a tiny bit out of phase with the corresponding input. CMOS IC's will have FET inputs, which have a gate capacitance, so you'll have an RC effect at the input of the circuit, which will delay the output.
You can see this on a scope by monitoring the input vs. the output of a digital circuit.

Answer 3

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Answer 4

Maybe you meant "slew" rate. Its the maximum rate at which an output can change and can be measured in units like volts per nanosecond.