How can I make a 1 second on, 1 second off circuit using PLC logic. I should have two timers in the circuit.?

Question

I'm not using AB PLC's. I know they have a system 1 second bit that will do this for me. But I have to make this happen using ladder logic.

Answer 1

The simplest way is to use the system's free-running clock using one of the bits in register S4. It will one on for one second and off for one second. That is how a professional would do it.

Here is how to do it with A-B logic. The logic is 4 rungs but it is hard to describe logic here because there is no graphic capability. [If you click on the left margin to highlight it, you can type in the rungs exactly as listed here using a space between instructions and ending the rung with the enter key. Then just clean them up with the graphics editor of your programming package.]

You need two TON timers and an output bit that you can latch/unlatch. You could use one-second timers with the preset at 1 but will get better accuracy if you use a .01 second timer with a preset of 100.

RUNG 1 Take the DN bit from timer T4:0 (XIC T4:1/DN) and parallel it with the first pass bit (XIC S:1/15) to latch on an output bit (OTL O:0/0) and to reset a second timer T4:1 (RES T4:1). That will initialize the output to be on.

RUNG 2: Take the inverted output bit (XIO O:0/0) and use it to run the timer T4:1 (TON T4:1) which runs for 1 second so the bit is on for that one second.

RUNG 3: Take the DN bit of timer 1 (XIC T4:0/1) and use it to unlatch the output (OTU O:0/0). Now the output will go off.

RUNG 4: Take the inverted output (XIO O:0/0) and use it to turn on the timer T4:0 (TON T4:0) which will run for 1 second keeping the output off for that time. After the second its DN bit will come on and the cycle will repeat from the action of the first rung.

Answer 2

You can make this 50% duty cycle circuit with one ordinary counter. The number of stages is related to the base time source, e.g., the clock you are using.

So chose a frequency that is divisible by a power of two. The lowest frequency you have that meets this need is good. Then make the counter. The number of stages is log(frequency)/log(2) and do not truncate, if there is a fraction boost the integer portion by one.

Then make the adder and use the MSB tap. Very simple.

Verilog for 1.048576 MHz

reg [19:0] cnt;

always@(posedge clk)
cnt <= cnt +1;


Note that if you only want the one output and asynchronous ripple counter fits this special case. Use the same number of DFFs. Connect the Q-out to the D-in on the same DFF for all DFFs. Then connect the Q-out to the CLK of the next stage. On the fist stage connect the clk to the CLK-in. Tap the last stage. Some teachers may not like this because there are very few places it can be used and they would rather not teach it, I understand this too but with one output having no synchronous requirement it fits best so I mention it.

Answer 3

Line 1: Open contact "examine if closed" which closes (goes true) when Timer #2 is done. After this contact parallel : Timer #1 and below parallel the Output "output energize" latch coil.

Line 2: Open contact which closes (goes true) when Timer #1 is done. After this contact parallel on one line Timer #1 and below parallel the Output coil un-latch.

Parallel a switch contact off one of the done contacts to start. This will cause the first timer to go true and start timing and energize the output. When the first timer times out the done contact in line 2 will close causing the timer 2 to start and causing the output coil to go true...........

Line 1: BST XIC T4:2/DN NXB XIC I:1.0/1 BND BST TON T4:1 1.0 1 0 NXB OTL O:1.0/1 BND

Line 2: XIC T4:1/DN BST TON T4:2 1.0 1 0 NXB OTU O:1.0/1 BND