how to reduce power in VLSI RTL design?

Answer 1

Lower the voltage.

Answer 2

Run the lowest possible clock frequency. If some parts of the circuit require fast clocking (DSP elements, for example) you have no choice. But don't run things any faster than you absolutely have to. And, as Jason said, go to a lower voltage logic family. Going from 3.3 V to 1.3 V in the logic cuts the power by almost 75% (it's proportional to V²)

HTH ☺


Doug