this question is about digital logic design :?

Question

Question: 1

What do you understand by Edge-Triggered Flip Flops? What is the difference between J-K and S-R Flip Flops? Also draw the logic symbols of Positive Edge-triggered and Negative Edge-Triggered of S-R and J-K Flip Flops.




Question: 2

Name some important properties/characteristics on which performance of flip flop is specified. Also define any two.

i need a detailed answer of these 2 questions .. i mean if u cud give the exact solution .. it wud b a gr8 help

Answer 1

J-K flip flops, see
http://www.play-hookey.com/digital/jk_nand_flip-flop.html
also
http://www.hobbyprojects.com/flip_flop/a_transistor_RS_flip_Flop.html

and a 20+ thousand others.


Doug

Answer 2

HAHAHA pune university? SE?? studying DS?

see edge triggering is done because if u leave a JK F/F with inputs 1-1 for enable input =1 for any period of time it changes erratically (toggle mode). edge triggering u put a cap between clock and enable i/p, connect to ground through resistor. this 1) cap becomes a differentiator and conducts only for when d/dt v!=0, so this produces +ve and -ve pulses for rising and falling edges.2)the resistor is there so that it goes to gound and creates voltage V so that i/p to terminal=+Vcc value around. diode is connected so that for -ve values of voltage diode is rev biased so only + edges are recieved as i/p. rest in techmax.