cascading logic gates?

Question

could anyone answer to this:
Explain what are the characteristics that must be considered when designing combinational circuits involving several gates connected in cascade.

Answer 1

The most important one are the glitches that can occur when there are differences in the propogation delay between gates.
It is possible to design logic circuits so that these glitches have no effect - can't remember what the technique is called, but involves overlapping fields in the Karnaugh maps.

Another characteristic to consider is the total propogation delay of the combinational circuit. The more logic gates you have in the path, the longer the delay

Answer 2

The specs of the IC's you are using determine how many inputs of subsequent devices can be driven when direct coupled. This is usually about 10 and is called the FAN OUT. The addition of a simple buffer stage can increase this spec.
If mixed devices are used then the total current used by the inputs of any stage must be less than the output limits of the preceding device. These current specs are also available for the series device you are using.
Depending on the types of devices used the power supply needs to be able to provide enough current for the total of all inputs used plus losses in the IC's.

Answer 3

A common figure that engineers calculate, and usually try to minimize is the "worst case propagation delay".