what is a gated delatch?

Question

microcontroller

Answer 1

In logic circuits, there is a flip flop called a D type. This device will latch a logical high or low when a clock edge occurs depending on which logic level is on its "D" input pin. It isn't called a gated D latch, but it could be gated by the gating the clock signal to it...the clock is only allowed to occur at a specific window of time by a gating signal. The gating signal and the clock would pass through a logical AND gate (for example) so that only when both are high is the high result sent to the D input of the flip flop (latch).

Now, if you really meant to call it a "delatch" instead of a D latch, then delatch is the process of reseting the flip flop. Most of them have a reset pin which acts asynchronously to reset the output state of the latch to 0 for Q and 1 for Q not.

Answer 2

a gated D-latch is a memory device flip flop. Its is to retain an output between clock cycles no matter what happens to the input and then replicate whatever is on its input when it gets the proper clock function. They can be either rising or falling edge triggered or level triggerd since it is a latch and not a true flip flop.