Is the HDL code generated by Xilinx System Generator synthesizeable to build an ASIC chip?

Question

As you know, the HDL code generated using Sysgen contains several Xilinx IPCore instantiation.
I want to know that if there is any chance to modify this HDL netlist not to have any information about Xilinx devices, so it can be layouted into an ASIC chip.

Answer 1

If it's standard HDL it certainly should be. But it has to be HDL, not the fuse-map code that you burn into the Xilinx PLA or it's support PROM.


Doug

Answer 2

yes, most definitely, only standard HDL though, it is one of the features that I was confused about when I was in college, so you should be fine.