how is transistor manufactured?

Question

with colour pictures.

Answer 1

I can't give you color pictures, but simply stated:

1) A pure silicon is mixed with impurities to make two different types of semi-conductor materials. They are called "P" and "N"
2) By use of chemical etching and depositing, they are sandwiched in PNP or NPN fashion.
3) Wires are attached and the assemly is encased in (usually) metal or epoxy.

Above is a very simple run-down of the process. There are two type of bipolar transistors, PNP and NPN. That's why they are sandwiched differently.

There are also other type of semi-conductor devices such as FET which is a "field effect transistors" that are manufactured in similar fashion. (and there are many other)

Is this what you wanted to know?

Answer 2

Little North Korean Guy Eats ,Little North Korean Shits Transistor

Answer 3

A transistor is basically an integrated circuit.


Manufacture
[edit]
Fabrication
Main article: Semiconductor fabrication.

The semiconductors of the periodic table of the chemical elements were identified as the most likely materials for a solid state vacuum tube by researchers like William Shockley at Bell Laboratories starting in the 1930s. Starting with copper oxide, proceeding to germanium, then silicon, the materials were systematically studied in the 1940s and 1950s. Today, silicon monocrystals are the main substrate used for integrated circuits (ICs) although some III-V compounds of the periodic table such as gallium arsenide are used for specialised applications like LEDs, lasers, and the highest-speed integrated circuits. It took decades to perfect methods of creating crystals without defects in the crystalline structure of the semiconducting material.

Semiconductor ICs are fabricated in a layer process which includes these key process steps:

Imaging
Deposition
Etching
The main process steps are supplemented by doping, cleaning and planarisation steps.

Mono-crystal silicon wafers (or for special applications, silicon on sapphire or gallium arsenide wafers) are used as the substrate. Photolithography is used to mark different areas of the substrate to be doped or to have polysilicon, insulators or metal (typically aluminium) tracks deposited on them.


Criss-crossing geometry of the layers of an ICFor a CMOS process, for example, a transistor is formed by the criss-crossing intersection of striped layers. The stripes can be monocrystalline substrate, doped layers, perhaps insulator layers or polysilicon layers. Some etched vias to the doped layers might interconnect layers with metal conducting tracks.
The criss-crossed checkerboard-like (see image above) transistors are the most common part of the circuit, each checker forming a transistor.
Resistive structures, meandering stripes of varying lengths, form the loads on the circuit. The ratio of the length of the resistive structure to its width, combined with its sheet resistivity determines the resistance.
Capacitive structures, in form very much like the parallel conducting plates of a traditional electrical capacitor, are formed according to the area of the "plates", with insulating material between the plates. Owing to limitations in size, only very small capacitances can be created on an IC.
More rarely, inductive structures can be simulated by gyrators.
Since a CMOS device only draws current on the transition between logic states, CMOS devices consume much less current than bipolar devices.

A memory device is the most regular type of integrated circuit; the highest density devices are thus memories; but even a microprocessor will have memory on the chip. (See the regular array structure at the bottom of the first image.) Although the structures are intricate – with widths which have been shrinking for decades – the layers remain much thinner than the device widths. The layers of material are fabricated much like a photographic process, although light waves in the visible spectrum cannot be used to "expose" a layer of material, as they would be too large for the features. Thus photons of higher frequencies (typically ultraviolet) are used to create the patterns for each layer. Because each feature is so small, electron microscopes are essential tools for a process engineer who might be debugging a fabrication process.


SEM image of an integrated circuit showing defects in the aluminium layer deposition (shown in cyan).Each device is tested before packaging using very expensive automated test equipment (ATE), a process known as wafer testing, or wafer probing. The wafer is then cut into small rectangles called dice. Each good die (N.B. die is the singular form of dice, although dies is also used as the plural) is then connected into a package using aluminium (or gold) wires which are welded to pads, usually found around the edge of the die. After packaging, the devices go through final test on the same or similar ATE used during wafer probing. Test cost can account for over 25% of the cost of fabrication on lower cost products, but can be negligible on low yielding, larger, and/or higher cost devices.

As of 2005, a fabrication facility (commonly known as a semiconductor fab) costs over a billion US Dollars to construct, because much of the operation is automated. The most advanced processes employ the following techniques:

The wafers are up to 300 mm in diameter (wider than a common dinner plate).
Use of 90 nanometer or smaller chip manufacturing process. Intel, IBM, and AMD are using 90 nanometers for their CPU chips, and Intel has started using a 65 nanometer process.
Copper interconnects where copper wiring replaces aluminium for interconnects.
Low-K dielectric insulators.
Silicon on insulator (SOI)
Strained silicon in a process used by IBM known as Strained silicon directly on insulator (SSDOI)