PCI-Express Connects to southbridge or northbridge?

Question

Previously, Northbridge (NB) connected with AGP, CPU, Memory and SouthBridge etc. and SB communicated with PCI, IDE etc. AGP is no more as we hav got PCIe. How does the PCIe communicate with CPU? Thruogh northbridge or southbridge.
Thanks in adv

Answer 1

"Intel envisions a single PCI Express controller talking to all external devices in the future, as opposed to the northbridge/southbridge solution used in current machines."

The PCIe physical layer consists of a network of serial interconnects. A hub on the mainboard acts as a crossbar switch allowing point-to-point device interconnections to be rerouted on the fly. This dynamic point-to-point connection behavior leads to parallelism since more than one pair of devices may communicate with each other at the same time. (In contrast, older PC interfaces had all devices permanently wired to the same bus; therefore, only one device could talk at a time.) This is similar to the difference between conversing over a telephone where you can only call one person at a time, and conversing in a meeting, where you can talk to a person beside you directly. The format also allows channel grouping, where multiple lanes are bonded to a single device pair in order to provide higher bandwidth.

The bonded serial format was chosen over a traditional parallel format due to the phenomenon of timing skew. Timing skew is a direct result of the limitations imposed by the speed of light: when an electrical signal travels down a wire, it does so at a finite speed. Because different traces in an interface have different lengths, parallel signals transmitted simultaneously from a source arrive at their destinations at different times. When the interconnection clock rate rises to the point where the wavelength of a single bit exceeds this difference in path length, the bits of a single word do not arrive at their destination simultaneously, making parallel recovery of the word difficult. Thus, the speed of light, combined with the difference in length between the longest and shortest trace in a parallel interconnect, leads to a naturally imposed maximum bandwidth. Serial channel bonding avoids this issue by not requiring the bits to arrive simultaneously. PCIe is just one example of a general trend away from parallel buses to serial interconnects. For other examples, see HyperTransport, Serial ATA, USB, SAS or FireWire. The multichannel serial design also increases flexibility by allowing slow devices to be allocated fewer lanes than fast devices.

PCIe is supported primarily by Intel, which started working on the standard as the Arapahoe project after pulling out of the InfiniBand system. PCIe is intended to be used as a local interconnect only. It was designed to be software compatible with the preexisting PCI standard, making the conversion of PCI cards and systems to PCI Express as simple as replacing the physical layer without requiring a change to the supporting software. The increased bandwidth on PCI Express has led to unification, as it is fast enough to replace almost all existing internal buses, including AGP and PCI. Intel envisions a single PCI Express controller talking to all external devices in the future, as opposed to the northbridge/southbridge solution used in current machines.

Unlike preceding PC expansion interface standards, PCIe is a point-to-point "bus". This type of connection removes the need for "arbitrating" the bus or waiting for the bus to free. This means that while standard PCI-X (133 MHz 64 bit) and PCIe x4 have roughly the same data transfer rate, PCIe x4 will give better performance if multiple device pairs are communicating simultaneously or if communication within a single device pair is bidirectional.

Answer 2

The northbridge typically handles communications between the CPU, RAM, AGP or PCI Express, and the southbridge The Southbridge, also known as the I/O Controller Hub (ICH) in Intel systems (AMD, VIA, SiS and others usually use 'southbridge'), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. As for the naming it derives from their locations

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Answer 5

It actually depends on which PCI Express. The x16 ones that are used for video cards connect to the northbridge, the slower x1 slots connect to the southbridge.

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Answer 7

The northbridge connects to the CPU, PCIe, and RAM.