English Deutsch Français Italiano Español Português 繁體中文 Bahasa Indonesia Tiếng Việt ภาษาไทย
All categories

4 answers

It's the clock enable pin
Look at
http://www.tranzistoare.ro/datasheets/90/108738_DS.pdf

The timing diagrams give a good functional look at what happens if pin 13 is not low. Low is enabled and high is disabled. When high the counter retains current state despite receiving clock pulses. This allows you to have an independent clock and control the operation of the counter through logic. An application for a pin like this is
"If state A then increment (#13=low), otherwise hold count(#13=high)."

j

2007-07-30 13:41:06 · answer #1 · answered by odu83 7 · 0 0

Clock enable. What's odd is that the datasheet calls it that, without a bar or a NOT as if it needs to be high for clock pulses to be counted, but the timing diagrams and the intro show it as if it has to be low for clocks to be counted.

http://www.fairchildsemi.com/ds/CD/CD4017BC.pdf

A bit of a contradiction there. But go by the timing diagram, it needs to be low for clocks to be counted. Most applications can just ground it.

2007-07-30 20:46:16 · answer #2 · answered by Gary H 6 · 0 0

Chip enable. See link.

2007-07-30 20:45:37 · answer #3 · answered by Vincent G 7 · 0 0

sorry left my digitech book at work whats it labeled as?

2007-07-30 20:36:37 · answer #4 · answered by j2 4 · 0 0

fedest.com, questions and answers