Instruction handling in caches, and using text files in test bench?

Question

I am an engineering student, and while I don't want someone to write a cache for me, I do need some clarification/reminders about caches and Verilog.

Here are my two main questions:

How does one handle instruction fetches in a cache? I know what happens with reads and writes in caches, but what about instruction fetches? I've looked online but so far haven't found anything I could use to better understand how to write this into the operation of my cache.

For example:

Your testbench must read memory accesses from a text file of the following format:
n address
Where n is
0 read data
1 write data
2 instruction fetch
The address will be a hex value. For example:
2 408ed4
0 10019d94
2 408ed8
1 10019d88
2 408edc

In essence, I'm asking how to deal with the "2"'s or instructions.

My second question is: How do I draw data from my din/text file into my testbench to then test my cache once testing begins? Then how does the testbench recognize each address (a carriage return, what code)?

"Ummm" is not a useful answer, no thanks.

Answer 1

umm