how to instantiate vhdl in system verilog?

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how to instantiate vhdl in system verilog?

i would like to instantiate vhdl uut in system verilog test bench.any thoughts.

2007-03-12 21:08:36 · 1 answers · asked by sundar_ece 1 in Computers & Internet ➔ Programming & Design

1 answers

If the program won't take VHDL you'll have to convert it to Verilog somehow. You could rewrite it. Or try a converter program, like vhd2vl. It might not translate all VHDL however.

2007-03-14 07:54:37 · answer #1 · answered by John Mahowald 5 · 0⤊ 0⤋