whats wrong with this VHDL code??

Question

library IEEE;
use IEEE.std_logic_1164.all;
entity test is
port (
a: inout STD_LOGIC_VECTOR(19 downto 0):="00000000000000000000";
clk:in STD_LOGIC
);
end test;
architecture test of test is
signal si:STD_LOGIC;
begin
process(clk)
begin
if(rising_edge(clk))then
si <= a(19);
a(19 downto 1)<= a(18 downto 0); --gave a=AB480h
end if;
end process;
end test;


I EXPECTED TO GET THE BITS IN a IN si ONE BY ONE DURING EACH CLOCK ..BUT WHAT I GOT WAS A '1' ALL THE TIME....PLS HELP ME OUT

Answer 1

i've only used vhdl xilinx boards for whole streaming signals, not bitwise. so, the only thing that i would suggest is to separate out your input variable to a smaller size and make your case logic more complex. I believe you can also separate out your signal and process sets, i remember doing that at one point in time. i guess that's a little vague, but without actually rewriting it it's hard to be specific.