what is the difference between flipflop and latch?

Answer 1

Flipflops and latches are both sequential circuit elements:

Latches pass data from input pin to output pin(s) ('D'->'Q', or whatever name), *whenever* the enable or clock signal ('EN','C','CK','CLK' etc.) is active (usually high).
Thus the effective edge of capture for a latch is the inactive edge (e.g. falling-edge of clock.)

Flipflops capture data from input pin to output pin(s) only on the active edge of clock. (This is implemented internally by a master-slave latch pair.)

[meodowla's answer is incorrect, he is confusing a latch with 'flipflop with asynchronous set and/or reset pin'.
Also, the designer has a free hand on whether latches are clocked or unclocked (subject to meeting setup- and hold-timing, clock skew and DFT requirements). The latch control signal can be positive-phase of clock, negative-phase of clock, a gated clock, or some other control signal]

Answer 2

In electronics, a latch remembers a previous state of a signal, and a flipflop alternates its setting on the occurrence of a signal.

Answer 3

A flip-flop input has to be pulsed momentarily to cause a change in flip-flop output, and the output will remain in that new state even after the input pulse has been removed.
The term 'latch' is used for certain flip-flops. It refers to non-clocked flip-flops, because these flip-flops 'lach on' to a 1 or a 0 immediately upon receiving the input pulse called SET or RESET.