give some example of risc and cisc processors?

Answer 1

CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clock
complex instructions Single-clock,
reduced instruction only
Memory-to-memory:
"LOAD" and "STORE"
incorporated in instructions Register to register:
"LOAD" and "STORE"
are independent instructions
Small code sizes,
high cycles per second Low cycles per second,
large code sizes
Transistors used for storing
complex instructions Spends more transistors
on memory registers

Answer 2

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These are type of processor architectures. Example x86 - is little endian (001 will be 1) RISC is big endian (001 will be 8) x86 is intels, Risc is motorola/PowerPC. So the type of binaries/program which run are different. Intel runs Linux/Windows RISC - Machintosh(apple computers- latest have intel also) Search on wiki you will get more information

Answer 3

risc processor:
The reduced instruction set computer, or RISC, is a CPU design philosophy that favors a simpler set of instructions that all take about the same amount of time to execute. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC.

The idea was originally inspired by the discovery that many of the features that were included in traditional CPU designs to facilitate coding were being ignored by the programs that were running on them. Also these more complex features took several processor cycles to be performed. Additionally, the performance gap between the processor and main memory was increasing. This led to a number of techniques to streamline processing within the CPU, while at the same time attempting to reduce the total number of memory accesses.







cise processors:
A complex instruction set computer (CISC) is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. The term was coined in contrast to reduced instruction set computer (RISC).

Before the first RISC processors were designed, many computer architects tried to bridge the "semantic gap" - to design instruction sets to support high-level programming languages by providing "high-level" instructions such as procedure call and return, loop instructions such as "decrement and branch if non-zero" and complex addressing modes to allow data structure and array accesses to be combined into single instructions. The compact nature of such a CISC ISA results in smaller program sizes and fewer calls to main memory, which at the time (the 1960s) resulted in a tremendous savings on the cost of a computer.

While they achieved their aim of allowing high-level language constructs to be expressed in fewer instructions, it was observed that they did not always result in improved performance. For example, on one processor it was discovered that it was possible to improve performance by not using the procedure call instruction but using a sequence of simpler instructions instead. Furthermore, the more complex the instruction set, the greater the overhead of decoding any given instruction, both in execution time and silicon area. This is particularly true for processors which used microcode to decode the (macro)instructions. In other words, adding a large and complex instruction set to the processor even slowed down the execution of simple instructions. Implementing all these complex instructions also required a great deal of work on the part of the chip designer, and many transistors; this left less room on the processor to optimize performance in other ways.

Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, and AMD and Intel x86 CPUs.

The term, like RISC, has become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first pipelined "CISC" CPUs, such as 486s from Intel, AMD, Cyrix, and IBM, certainly supported every instruction that their predecessors did, but achieved high efficiency only on a fairly simple x86 subset (resembling a non load/store "RISC" instruction set). Modern x86 processors also decode more complex instructions into series of smaller internal "micro-operations" which can thereby be executed in a pipelined (parallel) fashion, thus achieving high performance on a much larger subset of instructions.