what are two reasons to avoid clocking a flipflop from logic gate or from another flipflop?

Answer 1

one would be that it would be delayed by the FF or logic gate, and I guess the other would be that it is now an asynchronous clock. Another, if you are talking about FPGA's, is that there are special lines for clocks that go to all of the logic blocks, minimizing the delay time. If you put the clock through a FF, then it comes out on a regular line and can be routed however the program see's fit.