Why in 8085 microprocessor databus is mutiplexed only with lowo order address bus?

Answer 1

Tinku saab will this help

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-μm CMOS process implementing the ARMTM V.5TE instruction set is described. The core described is the first implementation of the Intel XScale MicroarchitectureTM. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm2 in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range

Answer 2

The data word is only 8-bit and its memory controller supports 16-bit address space